Logic Gate Simplifier: How to Minimize Digital Logic Circuits
About the Author
Marko Šinko
Co-Founder & Lead Developer, AI Math Calculator
A logic gate simplifier takes a digital circuit described by a Boolean function and rebuilds it with as few gates as possible. Feed it A·B·C + A·B·C' + A·B'·C + A'·B·C and it hands back A·B + A·C + B·C — the same truth table, but eight gates instead of four product terms feeding a wide OR. That difference is real silicon: fewer transistors, lower power, and a signal that settles faster. This guide is about the hardware side of simplification — counting gates, cutting propagation delay, and choosing between AND-OR, NAND, and NOR builds.
The tool above works two ways. You can type an expression, or you can define the function the way a hardware engineer usually meets it — as a truth table — and flip each output bit until it matches your spec. Either way it minimizes with the Quine–McCluskey algorithm, then reports the exact gate count, the logic depth, and what the circuit costs in NAND-only or NOR-only form.
Why Gate Count Is the Number That Matters
On paper a Boolean expression is just symbols. In hardware every operator becomes a physical gate, and every gate costs three things: area on the die, static and switching power, and delay. A two-input NAND in a typical standard-cell library is roughly four transistors. Shave four gates off a circuit that gets instantiated a million times across a chip and you have saved millions of transistors. That is why minimization isn't a tidiness exercise — it's a cost-reduction step that happens before anything gets fabricated.
There's a second, sneakier cost: delay. Signals don't cross a gate instantly. Each gate adds a propagation delay of tens to hundreds of picoseconds, and those delays add up along the longest path through the circuit — the number of gates a signal passes from input to output. We call that the logic depth, and it sets the maximum clock speed of the block. A circuit that's three gates deep can run faster than one that's six gates deep, even if both have the same total gate count.
Starting From a Truth Table, Not an Equation
Most real design problems don't arrive as a neat equation. They arrive as a specification: “the output is 1 for these input combinations and 0 for the rest.” That's a truth table, and it's why the calculator's truth-table mode exists. List every input combination as a row, mark the rows where the output is 1 (those rows are the minterms), and the minimizer does the rest.
Take a 3-input majority circuit — output 1 whenever two or more inputs are high. The minterms are rows 3, 5, 6, and 7. Written out the long way (canonical sum of products), that's four three-literal product terms: A'BC + AB'C + ABC' + ABC. Minimized, it collapses to AB + AC + BC. The canonical form needs four AND gates, a four-input OR, and three inverters; the minimized form needs three AND gates and one OR. If you want to see the full table that drives this, build it first with the truth table calculator and copy the minterms across.
A Worked Example: Cutting Both Gates and Delay
Consider A'·B·C + A·B'·C + A·B·C' + A·B·C again — the same majority function, written as four explicit minterms. Here's the before-and-after the simplifier reports:
| Metric | Original (4 minterms) | Minimized (AB + AC + BC) |
|---|---|---|
| AND gates | 4 | 3 |
| OR gates | 1 | 1 |
| Inverters | 3 | 0 |
| Total gates | 8 | 4 |
| Logic levels | 3 (NOT → AND → OR) | 2 (AND → OR) |
Half the gates and one fewer logic level. The lost inverter stage is the quiet win: because the minimized form never complements a variable, the signal skips an entire layer of delay. That's the kind of result that turns a circuit that barely meets timing into one with margin to spare. For the algebra behind how those minterms combine, the Boolean algebra simplifier walks each law step by step.
Building With NAND or NOR Only — and Why Designers Do It
Here's something that surprises newcomers: real chips are rarely built from AND, OR, and NOT gates. They're built mostly from NAND or NOR, because a single gate type is cheaper to fabricate and characterize, and NAND in CMOS is faster and smaller than AND (an AND gate is literally a NAND with an inverter bolted on). Both NAND and NOR are universal — any logic function can be built from one of them alone.
A minimal sum of products maps straight onto a two-level NAND-NAND network: one NAND per product term, one NAND combining them, plus an inverting NAND for each complemented input. A minimal product of sums maps the same way onto a NOR-NOR network. The calculator computes both counts so you can see which gate family is cheaper for your particular function — sometimes SOP wins, sometimes POS does, and it depends entirely on how many 1s versus 0s the truth table has.
SOP or POS? A Quick Decision Rule
Every function has a minimal sum of products and a minimal product of sums, and they describe the identical logic. The practical question is which one needs fewer gates in your technology.
- Few 1s in the truth table? Sum of products usually wins — you get a short OR of a handful of AND terms. Pair it with a NAND-NAND build.
- Few 0s in the truth table? Product of sums usually wins — a short AND of a few OR terms. Pair it with a NOR-NOR build.
- Roughly balanced? Compute both and compare gate counts directly. The difference is often one or two gates, and that can decide it.
If your design also evaluates conditions in software rather than silicon — say, simplifying a tangle of if conditions — the same minimization applies, and the Boolean algebra calculator is handy for evaluating specific input assignments as you go.
Mistakes That Quietly Inflate Your Gate Count
- Stopping at the canonical form. Writing one product term per minterm is correct but wasteful. Always minimize before you count — the canonical version can easily use twice the gates.
- Forgetting shared inverters. If A' appears in five terms, you still build one inverter and fan it out, not five. Counting an inverter per occurrence overstates the cost.
- Ignoring fan-in limits. A “single” eight-input OR rarely exists as one gate; it's built from a tree of two- or three-input gates, which adds depth. Minimal gate count on paper can hide real delay.
- Breaking De Morgan halfway. Converting to NAND-only,
(A·B)'isA' + B'— flip the operator and negate each input. Half-applying it produces a circuit that doesn't match the truth table. - Optimizing gate count while blowing past timing. The fewest-gate solution isn't always the fastest. If the block is on the critical path, trade a gate or two for a shallower depth.
Where a Logic Gate Simplifier Fits in Real Design Work
This isn't only a classroom exercise. Address decoders, multiplexer select logic, ALU control, and the state-decode logic in finite state machines all start as truth tables and get minimized before layout. Even in software, simplifying branch conditions reduces the number of comparisons the CPU runs. The skill transfers anywhere logic gets evaluated repeatedly. For the formal background on the tabular method this tool uses, the Quine–McCluskey algorithm entry is a solid reference, and you can sanity-check any single expression against the Boolean expression solver.
